Complex computing tasks such as processing file-access requests often require execution of hundreds of complex instruction set computer (CISC) instructions or even more reduced instruction set computer (RISC) instructions. File-access requests may be received from a variety of source over a network such as the Internet, and these requests may be in a variety of formats for the many different protocols in use. These requests may be contained in messages that include a header than must be parsed to locate critical information, such as a file name or handle for the requested resource.
The parsing of the header is made more difficult by the use of variable-length strings. The file handle may include a file name, which may be stored as a variable length string. Locating fields in the header after such a variable-length field requires knowledge of the string length, which may not be known until after the variable-length string field is read.
The parent application disclosed a new type of computer architecture ideally suited for processing such file-access requests. Rather than executing lower-level CISC or RISC instructions, the new architecture executes function-level instructions. This architecture that executes these functional-level instructions is called Functional-level instruction-set computing (FLIC).
The present application is directed to FLIC copy instructions. The functional-level copy instruction can copy variable-length data between a variety of computing resources on a FLIC processor, such as between general-purpose registers (GPR's), dynamic-random-access memory (DRAM), static random-access memory (SRAM), variable-length execution buffers, input and output buffers, and immediate tables.
FIG. 1 is a diagram of a FLIC processor. FLIC processing engines 20 include one or more slices of FLIC engine 60. Each slice can process a different request, allowing for parallel processing of requests from different sources.
Copy/move unit 58 moves data among computing resources, such as from input buffer 42 to FLIC engine 60 and then to output buffer 44. Copy/move unit 58 also allows FLIC engine 60 to read and write memory resources such as global block 40. Global block 40 can include DRAM 45, SRAM 43, and immediate table 48.
SRAM 43 can include state memory referred to by a state identifier copied from state input buffer 41 into execution buffers 54.
Requests from I/O, network interfaces, general-purpose processing engines, and/or co-processors are received into input buffer 42. These requests may include messages that have variable-length strings and require parsing, such as file-access commands. Copy/move unit 58 copies parts of requests stored in input buffer 42 to FLIC engine 60, and writes replies to output buffer 44. The replies in output buffer 44 can be sent to I/O ports, general-purpose processing engines and/or co-processors.
FLIC engine 60 includes a variety of specialized execution hardware, such as processing units 50. A vector compare unit in processing units 50 can compare variable-length strings, assisting in parsing a request message. Processing units 50 can also include an arithmetic-logic-unit (ALU), branch, bitmap processing units, security-acceleration units, and a variety of other kinds of units.
Immediate table 48 contains pre-defined constants, structure templates, and rule values that can be used by instructions. During execution, an immediate value can be copied from immediate table 48 to processing units 50 or to registers 46, or to execution buffers 54.
Data operands can be stored in fixed-length registers 46, which are architecturally-visible general-purpose registers. Variable-length operands can be stored in execution buffers 54. A register in fixed-length registers 46 can contain a pointer to the location of the variable-length operand in execution buffers 54. Another register in fixed-length registers 46 can store the length of the variable-length operand or contain a pointer to the end of the variable-length operand in execution buffers 54.
Multiple contexts can be supported. Multiple sets of fixed-length registers 46 and execution buffers 54 can be provided, with a different register set assigned to each context. Input buffer 42 can likewise support multiple contexts with separate storage areas for each context. Rapid context-switching can be supported by switching the current input buffer, register, and execution-buffer set being used for execution.
Expansion buffer 52 provides additional storage space for execution buffers 54. When additional storage space is needed by a context to store variable-length operands, additional space can be allocated to that context's execution buffers 54 from expansion buffer 52.
A context is allocated to process a request message. One set of fixed-length registers 46 and execution buffers 54 is allocated for processing a message. A context may refer to a relevant state using a state ID. A context's current state ID can be stored in each context's execution buffer 54. The state ID is a pointer to more detailed state information contained in a state memory such as in SRAM 43 of global block 40. State parameters such as a current state in a sequence of states can be copied from state memory in SRAM 43 to fixed-length registers 46 or execution buffers 54 when needed for execution. Both global and local state ID's can be supported.
Instruction fetch, decode, and dispatch units (not shown) can exist on each slice of FLIC engine 60, or can be shared among all slices.
What is desired is a functional-level copy instruction that can copy variable-length data. A FLIC copy instruction that can copy data among a variety of resources, such as registers, input, output, and execution buffers, and global block SRAM or DRAM memories, is desirable. An extension of the copy instruction for performing validation of the data being copied is also desired.